LVPECL, LVDS, HCSL signal formats are widely used in high speed data communications, especially for signal frequencies between 20 MHz and 1 GHz. The CML signal format is commonly used internally within high-speed devices. There is a need for a driver interface that can accept a CIVIL format signal and output that signal in a different format, such as LVPECL, LVDS, or HCSL. The driver interface should be able to select the appropriate output format under the control of a simple logic input. The driver interface needs to be able to handle the different loading and powering conditions of the various formats. In general terms, LVPECL requires an 800 mV swing with a common mode voltage of 2V, LVDS requires a 400 mV swing with a common mode voltage of 1.2 V and HCSL requires steering a current of 15 mA alternately between the positive and negative outputs.
FIG. 1 is a schematic diagram of a conventional multi-format driver interface. There are three separate output driver stages in parallel, corresponding respectively to LVDS, HCSL, and LVPECL, driven by the CML-to-Full-Swing pre-driver module. The output format is selected by an input formatting_logic_in.
In CIVIL logic, the transistors are never in saturation. The input/output voltages have a small swing, which is converted into a full swing in the CIVIL-to-Full-Swing pre-driver module to drive, via data outputs DA/DA′, DB/DB′, and DC/DC′, transistor pairs having their respective gates coupled to connection lines AA′, BB′, CC′ respectively.
Connection lines AA′ are connect to the gates of the P-channel transistors used for LVDS and HCSL. Connection lines BB′ connect to the gates of the P-channel transistors used for HCSL. The connection lines CC′ connect to the gate of N-channel transistor used for LVPECL and LVDS.
The transistor pairs, which are the source transistors providing the necessary current for the relevant output signal format, are shown in FIGS. 2 to 4 as QP1/QP2, QP3/QP4, and QN3/QN4, where N and P refer to the channel type of the transistor. Both the transistor pairs QP1/QP2 and QN3/QN4 coupled to connection lines AA′ and CC′ are double-loaded, which means that drive more than one physical load. The pair QP1/QP2 is loaded for both LVDS and HCSL. The pair QN3/QN4 is loaded for LVDS and LVPECL. This is a drawback from the point of view of power consumption and signal conditioning, especially in high speed applications where the rise and fall time of the signal is critical to noise performance. More loading means degradation of the rise and fall time, and thus noise performance. In order to maintain a fast rise fall and time the transconductance (gm) of the driver stage needs to be improved, either by increasing its size (larger die area), or by increasing its biasing current (power consumption), and more likely both. This approach is not efficient in terms of both area and power.
FIG. 2 is an example of a prior art LVPECL driver, FIG. 3 is an example of an LVDS driver, and FIG. 4 is an example of a prior art HCSL driver, which can all be combined as shown in FIG. 1 into a multi-format interface.
While the LVDS and HCSL drivers employ current loops, a typical prior art LVPECL driver consists of a CML stage with a source (e.g. emitter) follower. Conventional wisdom is that a source follower is a necessary component of an LVPECL driver. As a result it is difficult to combine an LVPECL driver with current loop drivers, such as LVDS and HCSL because large switches are required to turn off the source follower of the LVPECL driver, leading to an expensive design in terms of die area.
In the prior art, the output loading of the arrangement of FIG. 1 can be described as follows:
LVPECL
QN1,QN2 (intrinsic)
QP1,QP2,QP3,QP4 (from HCSL)
QP1,QP2,QN3,QN4 (from LVDS)
HCSL
QP1,QP2,QP3,QP4 (intrinsic)
QP1,QP2,QN3,QN4 (from LVDS)
QN1,QN2 (from LVPECL)
LVDS
QP1,QP2,QN3,QN4 (intrinsic)
QP1,OP2,OP3,OP4 (from HCSL)
QN1,QN2 (from LVPECL)
In the prior art interface, the filtering of the biasing current for noise considerations is achieved by components RP/CP and RN/CN for LVDS, by components RN/CN for LVPECL, and by RP/CP for HCSL. Components RP/CP and RN/CN take up a large die area
The control of the biasing point is achieved by transistor pairs QP1/QP2 and QN3/QN4 for LVDS; QN3/QN4 for LVPECL; and QP1/QP2 and QP3/QP4 for HCSL. The pair QP1/QP2 can be optimized for both LVDS/HCSL, and the pair QP3/QP4 can be optimized for HCSL with the appropriate choice of the input driving signal from the CML-to-Full-Swing module. The input driving signal should have the right input slew rate (i.e. good rise and fall time), and steady state voltage levels (VH and VL, respectively corresponding to the logic 1 and logic 0 states).
The transistor pair QN3/QN4 cannot be optimized for both LVPECL and LVDS due to their different output common mode voltages. The VH and VL input driving signals cannot be optimized for both formats, so in order to have good noise performance, a separate driving stage for LVDS and LVPECL is required, thus making the die area larger and the power consumption greater.